/**
 ** 执行-写回中继器
**/

module EXE_MEM (
    input wire clk,                      //时钟信号
    input wire rst,                      //复位信号（暂无使用）
    input wire [31:0] alu_r_in,          //运算器结果输出
    input wire [2:0] dm_rd_ctrl_in,      //数据存储器读控制信号
    input wire [1:0] dm_wr_ctrl_in,      //数据存储器写控制信号
    input wire reg_write_en_in,          //寄存器写使能信号
    input wire [1:0] reg_write_sel_in,   //寄存器写选择信号
    input wire [31:0] now_inst_in,       //当前执行的指令
    input wire [31:0] pc_in,             //当前的PC
    input wire [31:0] reg_r2_in,         //

    output reg [31:0] alu_r_out,         //运算器结果输出信号
    output reg [2:0] dm_rd_ctrl_out,     //数据存储器读控制信号输出
    output reg [1:0] dm_wr_ctrl_out,     //数据存储器写控制信号输出
    output reg reg_write_en_out,         //寄存器写使能信号输出
    output reg [1:0] reg_write_sel_out,  //寄存器写选择信号输出
    output reg [31:0] now_inst_out,      //指令输出 
    output reg [31:0] pc_out,            //指令地址输出
    output reg [31:0] reg_r2_out         //
);

    //在上升沿，完成输入信号和输出信号的映射，此指令进入下一流水级
    always @(posedge clk) begin
        dm_rd_ctrl_out <= dm_rd_ctrl_in;
        dm_wr_ctrl_out <= dm_wr_ctrl_in;
        now_inst_out <= now_inst_in;
        reg_write_en_out <= reg_write_en_in;
        reg_write_sel_out <= reg_write_sel_in;
        pc_out <= pc_in;
        alu_r_out <= alu_r_in;
    end
endmodule